Topic

Small is Beautiful – Temporal Accelerators for Embedded FPGAs

Christopher Cichiwskyj

Christopher Cichiwskyj, Gregor Schiele

University of Duisburg-Essen

 

Abstract:

 

When the complexity of a problem rises, its solution needs more hardware resources. A usual way to solve this is to use larger processors and add more memory. When using Field Programmable Gate-Arrays (FPGAs), which can instantiate arbitrary circuit designs, a larger, more costly and power hungry chip is used. In this extended abstract we propose a different approach, namely to split the problem into a graph of interdependent smaller tasks and to reconfigure a small FPGA during runtime to execute each of these tasks efficiently sequentially. This can result in cheaper and more energy efficient systems that can execute very complex problems locally.

 

 

 

 

Discussion Room: Small is Beautiful – Temporal Accelerators for Embedded FPGAs

 

christopher.cichiwskyj@uni-due.de

Leave a Reply

Your email address will not be published. Required fields are marked *